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IEEE Workshop on FPGAs for Custom Computing Machines
April 5-7, 1993 The Inn at Napa Valley, Napa, California
PURPOSE:
To bring together researchers interested in the use of Field Programmable
Gate Arrays as computing elements to present recent work. While papers
of a theoretical nature are welcomed, it is anticipated that this
workshop will focus primarily on the current opportunities and problems
in this new and evolving technology for computing. A proceedings will
be published by the IEEE Computer Society; this workshop is sponsored
by the IEEE Computer Society and the TC on Computer Architecture.
SHORT PAPERS OR ABSTRACTS (10 pages) SHOULD BE SUBMITTED BEFORE
JANUARY 9, 1993 TO ONE OF THE TWO CONFERENCE CO-CHAIRS.
CoChairs: Ken Pocek (west coast) Duncan Buell (east coast)
Intel Supercomputing Research Center
Mailstop SC1-03 17100 Science Drive
3065 Bowers Avenue Bowie, Maryland 20715
Santa Clara, CA 95052 301-805-7372
408-765-2363 301-805-7602 (fax)
408-765-2949 (fax) duncan at super.orgkpocek at sc.intel.com
ORGANIZING COMMITTEE:
Lynn Abbott , VPI Fred Furtek, Concurrent Logic
Jeffrey Arnold, SRC Leon Maissel, IBM
Peter Athanas, VPI Richard Newton, U Cal-Berkeley
Apostolos Dollas, Duke U Jonathan Rose, U Toronto
Tom Kean, Algotronix Steve Trimberger, Xilinx
Wally Kleinfelder, SRC David Van den Bout, N. Carolina State U
SOLICITATION::
Papers are solicited on all aspects of the use or applications of
(usually multiple) FPGAs as (usually reconfigurable) computing
elements in attached or special purpose processors or coprocessors,
especially including but not limited to
*** coprocessor boards for augmenting the instruction set of
general purpose computers;
*** attached processors for specific purposes (e.g. signal
processing) or general purposes;
*** languages for programming FPGA-based computers;
*** tools and environments for programming FPGA-based computers;
*** application domains suitable for FPGA-based computers;
*** architecture emulation using FPGA-based computers.
There also will be panel discussions including representatives from
major vendors on future software and hardware for FPGA based systems.
Individuals wishing to be put on an email list for further information
about this workshop should send email with name, regular mail address,
and email address to Duncan Buell.
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REGISTRATION AND HOTEL INFORMATION
IEEE Workshop on FPGAs for Custom Computing Machines, April 5-7, 1993
The Inn at Napa Valley, 1075 California Blvd., Napa, California 94559
707-253-9540, 800-433-4600, 707-224-7708 (fax)
PLEASE TYPE OR PRINT
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The registration fee schedule is as follows. The deadline for
preregistration is March 12, 1993. Regular (nonstudent)
registration includes a copy of the proceedings and lunch on
Monday and Tuesday, April 5 and 6.
Preregistration Onsite Registration
IEEE Members 200 245
Non-Members 265 325
Students 75 90
All rates are U. S. dollars. Checks should be made payable to
IEEE FCCM Workshop. Checks and registration forms should be
mailed to IEEE FCCM Workshop, c/o Duncan Buell, Supercomputing
Research Center, 17100 Science Drive, Bowie, Maryland 20715 (USA).
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REGISTRATION AND HOTEL INFORMATION (page 2)
IEEE Workshop on FPGAs for Custom Computing Machines, April 5-7, 1993
The hotel rate is $119 per day single or double occupancy.
This includes full breakfast each morning and reception with
wine tasting each evening. Rooms are 2-room suites with
microwave, coffee maker, and refrigerator.
Hotel reservations should be made directly with the hotel.
The workshop is scheduled to run all day Monday and Tuesday
April 5 and 6 and end at noon on Wednesday April 7.