F architecture?

Thomas J. Merritt tjm at netcom.com
Wed Sep 9 14:19:54 EST 1998

In article <35f6c99b.0 at news.victoria.tc.ca>, Mentifex <mentifex at scn.org> wrote:
|Bill Broadley <bill at proto.math.ucdavis.edu> posted on 9 Sep 1998:
|> Any comments on the F-architecture at:
|> http://siva.usc.edu/~brion/f/
|> From the architecture page:
|> 64-bit datapath and address space            
|> Speculative and parallel execution pipelines     
|> Three cache levels:
|> L0: 8KB, 4-ported, line lockable - internal            
|> L1: 64KB data plus 64KB intruction (dual ported, line lockable) -
|> L2: > 1MB (possibly!) - external (on motherboard)
|> No internal registers - this is a memory-to-memory processor. [...]

The performance of an F-architecture processor (given the current
vague specifications on the above web site) would likely be poor.  The
primary problem is that the described addressing model creates aliases
for the contents of the L0 cache which is expected to take the place of
a register file.  These aliases will complicate the pipeline bypass/forwarding
logic.  The result will be a longer clock period and/or longer pipeline
latency for operations relative to a register based architecture.  There isn't
much clue given as to how they intend to avoid these effects.  Given the
lockablity of the L0 cache, it mighe be possible to implement some sort of
cache line renaming mechanism.  

TJ Merritt
tjm at nospam.codegen.com

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